1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and particularly to a semiconductor memory device, such as a DRAM and a VRAM, capable of verifying whether a redundant circuit is being used or not.
2. Description of the Background Art
FIG. 9 is a block diagram showing the whole structure of a conventional video random access memory (hereinafter referred to as VRAM). Referring to FIG. 9, the VRAM includes a memory cell array 1, a row decoder 2, a column decoder 3, an address buffer 4, address terminals 5, a random input/output buffer 6, and random input/output terminals 7.
Memory cell array 1 includes a plurality of memory cells arranged in a matrix constituted of rows and columns. Row decoder 2 selects any one row of memory cell array 1 according to an address signal from address buffer 4. Column decoder 3 selects an arbitrary column of memory cell array 1 according to an address signal from address buffer 4. Address buffer 4 converts an external address signal A0-An from address terminal 5 into the internal address signal. Address terminals 5 are for externally inputting the address signal A0-An. Random input/output buffer 6 applies a data signal WIOi from random input/output terminals 7 to a memory cell of memory cell array 1 selected by row decoder 2 and column decoder 3, or applies a data signal from a memory cell of memory cell array 1 selected by row decoder 2 and column decoder 3 to random input/output terminals 7. Random input/output terminals 7 are for applying the externally applied data signal WIOi to random input/output buffer 6, or providing a data signal from random input/output buffer 6 to the outside.
The VRAM further includes a data transfer bus 8, a serial register 9, a serial selector 10, a serial clock buffer 11, a serial clock terminal 12, a serial input/output buffer 13, serial input/output terminals 14, a quote signal generating circuit 15, and a quote terminal 16.
Data transfer bus 8 transfers data between a row of memory cell array 1 selected by row decoder 2 and serial register 9. Serial register 9, which includes the same number of register elements as that of memory cells constituting one row of a memory cell array 1, stores data transferred from memory cells constituting one row of memory cell array 1 in the register elements to divide the data into data stored in the upper half of the register elements and data stored in the lower half of the register elements, and serially provides respective data.
Serial register 9 also stores data applied from serial input/output buffer 13 in the register elements, and transfers the data to memory cells constituting one row of memory cell array 1 through data transfer bus 8. Serial selector 10 selects the register elements of serial register 9 one by one in response to a serial clock SC from serial clock buffer 11, so that data stored in the register elements are provided.
Serial clock buffer 11 applies the serial clock SC from serial clock terminal 12 to serial selector 10. Serial input/output buffer 13 applies serial data from serial register 9 to serial input/output terminal 14, or applies serial data SIOi from serial input/output terminal 14 to serial register 9.
Quote signal generating circuit 15 generates a quote signal QSF indicating which of the data stored in the upper side of the register elements and in the lower side of the register elements is now being provided, based on a counter signal CT from serial selector 10, to provide the same to quote terminal 16. Quote terminal 16 is for providing the quote signal QSF to the outside.
The VRAM further includes a clock generator 17, and external control terminals, such as a specific function select terminal 18 and address strobe control terminals 19.
Clock generator 17 generates an internal control signal based on external control signals DSF, *RAS, *CAS, *DT/*OE, and *WB/*WE from the external control terminals. Specific function select terminal 18 is for externally inputting the specific function select signal DSF for selecting a specific function, such as block write, write-per-bit, and split data transfer. Address strobe control terminal 19 is for externally inputting the external control signal *RAS or *CAS indicating a timing to strobe a row address or a column address to row decoder 2 or column decoder 3. Here, the * mark attached in front of a signal indicates that the signal follows the negative logic (is in the active state when it is at an "L (logical low)" level).
The VRAM further includes a fuse circuit 20 and a redundant circuit 21 and 1a. Referring to FIG. 10, fuse circuit 20 generates a redundant signal *RDD for activating redundant circuit 21. Fuse circuit 20 including a fuse F generates the redundant signal *RDD of an "L" level by fuse F being disconnected by laser, when redundant circuit 21 is used. The redundant circuit includes spare memory cells 1a. When any defective memory cell exists among normal memory cells, the address of the defective memory cell is programmed in advance, so that the redundant circuit activates one of spare memory cells 1a in place of the defective memory cell.
FIG. 11 is a schematic diagram showing fuse circuit 20 and a part of redundant circuit 21. Referring to FIG. 11, where redundant circuit 21 is used, fuse F of fuse circuit 20 is disconnected, so that the redundant signal *RDD at an "L" level is provided. A program circuit 21a which is a part of redundant circuit 21 is activated by the redundant signal *RDD. Program circuit 21a has the address of a defective memory cell programmed in advance, so as to provide a select signal SL indicating that a spare memory cell is selected in place of the defective memory cell, on application of a decode signal CQi of a specific column address activating the defective memory cell.
As described above, the redundant circuit includes spare memory cells 1a constituting several rows and/or several columns, whereby, in the case of presence of any defective memory cell in memory cell array 1, a spare memory cell is selected in place of the defective memory cell on application of an address signal selecting the defective memory cell. Accordingly, even if any defect exist in a part of memory cell array 1, memory cell array 1 can be used as a non-defective one.
In the case of any general fault in a VRAM, verification might be required whether the fault is caused by use of a redundant circuit or not. Although a microscope may be employed for externally verifying whether fuse F of fuse circuit 20 is disconnected or not, it cannot be used in mold products.
A method of verifying whether fuse F of fuse circuit 20 is disconnected or not without a microscope is disclosed in U.S. Pat. No. 4,480,199. Briefly, in this method, considering the fact that a current flowing throughout a device is decreased when a fuse is disconnected, it is determined whether a redundant circuit is being used or not by applying a higher voltage than a normal power supply voltage to the device, and detecting a current flowing therethrough at that time.
In such a method, however, since a higher voltage than a normal power supply voltage is applied, a current flowing therethrough is disadvantageously increased. In addition, it is disadvantageously increased as the number of fuse circuits increases. Moreover, since currents flowing through a fuse vary, it is difficult to accurately determine whether the fuse is disconnected or not.
In order to solve such a problem, a semiconductor memory device is disclosed in Japanese Patent Laying-Open No. 63-217600, which is constituted so as to read data as to disconnection of a fuse through an output buffer for outputting data from a memory cell array.
FIG. 12 is a schematic diagram of a circuit showing the main part of such a semiconductor memory device. Referring to FIG. 12, the semiconductor memory device includes a memory cell array 1, an output buffer circuit 22, a fuse circuit 23, a power supply initialize circuit 24 and transfer gates 25 and 26.
Output buffer circuit 22 normally outputs data from memory cell array 1 to the outside. An output node N2 of fuse circuit 23 corresponding to fuse circuit 20 described above is at an "L" level when a fuse F is not disconnected, while it is at an "H (logical high)" level when fuse F is disconnected. Power supply initialize circuit 24 generates a pulse signal .phi. upon sensing power-on. Transfer gates 25 and 26 are alternately rendered conductive, or non-conductive in response to the pulse signal .phi. from power supply initialize circuit 24.
In this semiconductor memory device, disconnection of fuse F can be verified without increasing a current flow throughout the device. Immediately after power-on, however, respective nodes and transistors are so unstable that disconnection of fuse F cannot be verified accurately. Additionally, since the pulse signal .phi. generated by power-on is utilized, turn-off of power is unpractically required for another verification of disconnection.